Imec & Cadence Tape Out Industry’s First 3nm Test Chip

Nanotechnology research centre imec has taped out what it says is the industry’s first 3nm test chip. The project, in association with Cadence, was completed using design rules focused at EUV and 193nm immersion lithography, along with Cadence’s Innovus and Genus software suites.. The tape out leads they way into a new chip area.

Picture Source: Semiconductor Engineering